1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an electrically erasable programmable non-volatile semiconductor memory (EEPROM) having bit line selection transistors arranged at a cell array end.
2. Description of the Related Art
In a mass NAND-type EEPROM configuration, bit lines arranged at a fine pitch are divided into odd and even ones, and either one of them is selectively connected to a sense amp. In this case, bit line selection transistors are arranged in a cell array at bit line ends to select odd and even bit lines.
FIG. 13 shows a configuration covering from a cell array 1 to a sense amp 2 in such the NAND-type EEPROM, focusing attention on odd bit lines BLo (BLo0<k>–BLo7<k>) and adjacent even bit lines BLe (BLe0<k>–BLe7<k>). There is an arrangement region 3 for bit line selection transistors Q0–Q15 between the cell array 1 and the sense amp 2. The cell array 1 comprises NAND cell units U arrayed. Each unit includes plural (16 in the shown example) non-volatile memory cells MC0–MC15 serially connected. Each NAND cell unit U has one end connected to the bit line BLo or BLe via a selection transistor S1 and the other end connected to a common source line CELSRC Via a selection transistor S2.
The memory cells MC0–MC15 have control gates respectively connected to word lines WL0–WL15, which are arranged to intersect the bit lines BLo and BLe. The selection transistors S1 and S2 have gates connected to selection gate lines SGD and SGS, which are arranged in parallel with the word lines. The ends of the bit lines BLo and BLe in the cell array are connected, via the bit line selection transistors controllable by selection signals BLSo and BLSe, to common sensing bit lines SBL, which are connected to the sense amp 2. For example, the bit lines BLo0<k> and BLe0<k> are connected via the bit line selection transistors Q0 and Q1 to the common sensing bit line SBL0<k>.
The bit line selection transistors Q0–Q15 are required to consist of a high voltage transistor because a high erasing voltage is applied to the bit line during data erase. This situation is specifically described. When data is written in the NAND-type EEPROM, the p-type well is held at 0V and a write voltage of approximately 20V is applied to the selected word line to inject electrons from the channel region into the floating gate of the selected memory cell. This results in a higher threshold of the memory cell in a written state (for example, the state of “0” data). On the other hand, data is erased in a block batch of cells sharing the p-type well. During data erase, while all word lines in the cell block are held at 0V and the bit lines are floated, an erase voltage of approximately 20V is applied to the p-type well to discharge the charges from inside the floating gate of the memory cell to the substrate. This results in a lower threshold of the memory cell in an erased state.
During data erase, the n-type diffusion layer connected to the bit line is forward biased relative to the p-type well. Therefore, the erase voltage of 20V may appear even on the floating bit line. The bit line selection transistors are formed in another p-type well different from the p-type well in the cell array 1, and are isolated from the p-type well in the cell array 1. When the voltage on the bit line is elevated up to 20V, however, a junction breakdown may possibly arise between the n-type source/drain diffusion layer of the bit line selection transistor and the p-type well, resulting in destruction of peripheral circuits. For the purpose of protection of the peripheral circuits, the bit line selection transistor should consist of a high voltage transistor.
As described above, the need for the high-voltage bit line selection transistors may add constrains to downsize them. Therefore, when the bit lines are arranged at a much finer pitch in the cell array 1, the layout of bit line selection transistors causes a problem.